Welcome to JJEM: A Multi-Disicplinary Journal of JNNCE, Shimoga

JJEM Eight Issue - Volume 4 Number 2 -2020

Volume 4, Issue 2

Development of Flexible Verification Environment for AMBA APB

Published:    2021-03-30


Nithin H V,  Kunjan D. Shinde


The SoC (System on Chip) uses AMBA (Advanced Microcontroller Bus Architecture) as an on chip bus. APB (Advanced Peripheral Bus) is one of the components of the AMBA bus architecture. APB is low bandwidth and low performance bus used to connect the peripherals like UART, Keypad, Timer and other peripheral devices to the bus architecture. This paper introduces the AMBA APB bus architecture design. The design is created using the verilog HDL and is tested by a System verilog test- bench. This design is verified using SV. A reuse based methodology for SoC design has become essential in order to meet these challenges. The work embodied in this paper presents the design of APB Protocol and the Verification of slave APB Protocol. Coverage analysis is a vital part of the verification process; it gives idea that to what degree the source code of the DUT has been tested. The functional coverage analysis increases the verification efficiency enabling the verification engineer to isolate the areas of untested function. The design and verification IP is built by developing verification components using Verilog and System Verilog respectfully with relevant tools such as Questasim and Cadence, which provides the suitable building blocks to design the test environment.